Foundation Lab

Distributed Training: Data, Tensor & Pipeline Parallelism

Large models REQUIRE distributed training—no single GPU can hold GPT-4 class models

Concept 50 of 100EfficiencyPhase 9

#50DistributedEfficiency

key equation\text{Memory per GPU} \approx \frac{\text{Model} + \text{Optimizer}}{\text{Parallelism degree}}

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Keep the equation fixed; move through the evidence.

Concept 50 of 100DistributedEfficiency / Phase 9: Advanced architectures & generation

Current question

Communication is often the bottleneck: AllReduce time can exceed compute time at scale

\text{Memory per GPU} \approx \frac{\text{Model} + \text{Optimizer}}{\text{Parallelism degree}}

PredictionCommit before the demo.

Ask what should change when the equation is manipulated, then let the visualization test that expectation.

EvidenceCompare local witness and source.

Use the runnable panel, the key equation, and canonical papers as separate forms of evidence for the same object.

InvariantName what survives notation changes.

The useful learning product is the reusable mechanism you can carry into another model, paper, or engineering tradeoff.

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Large models REQUIRE distributed training—no single GPU can hold GPT-4 class models
3D parallelism (data + tensor + pipeline) is how 100B+ models are trained
Understanding communication patterns explains why some architectures scale better than others

What is still poorly explained in textbooks and papers:

Communication is often the bottleneck: AllReduce time can exceed compute time at scale
ZeRO stages trade memory for communication: ZeRO-3 is most memory-efficient but slowest
Pipeline bubbles waste compute: micro-batching (1F1B schedule) minimizes idle time

If you want intuition first, start with the key equation and the visualization. Come back here for the full walkthrough.

Key Equation

\text{Memory per GPU} \approx \frac{\text{Model} + \text{Optimizer}}{\text{Parallelism degree}}

Data parallelism: Each GPU holds full model, processes different batches:

\nabla L = \frac{1}{N}\sum_{i=1}^{N} \nabla L_i \quad \text{(AllReduce)}

Tensor parallelism: Split matrix multiplies across GPUs:

Y = XW = X[W_1 | W_2] = [XW_1 | XW_2] \quad \text{(column split)}

Pipeline parallelism: Split layers across GPUs, micro-batch for efficiency:

\text{GPU}_i: \text{layers } [l_i, l_{i+1})

ZeRO partitions optimizer states, gradients, parameters across ranks.

Shoeybi et al.2020arXiv

Rajbhandari et al.2020SC

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